MOS transistors are widely used in both analog and digital circuits, such as amplifiers, and analog-to-digital and digital-to-analog converters. Complementary metal-oxide-semiconductor (CMOS) field-effect transistors formed by pairs of N and PMOS transistors, are particularly widely used in large scale digital circuits, such as microprocessors, memory devices and gate arrays, as they have high performance and consume very little electric power.
A typical field-effect transistor comprises a substrate, at least one source disposed on the substrate, at least one drain disposed on the substrate, and at least one gate disposed on the substrate between the source and the drain. The gate typically comprises a conducting layer, such as a metal or a semiconductor layer, or the combination thereof, which is insulated from the source, the drain and the substrate by a dielectric layer, such as an oxide or a nitride layer.
The increasingly strong demand for higher speed, larger scale integrated circuits with higher component density and higher drive current has necessitated smaller and smaller component sizes. Presently the length of the channel of a MOS transistor has reached the submicron regime.
Unfortunately, the conventional submicron MOS transistors suffer from the problem of the short channel induced saturation threshold voltage (Vts) roll-off or the reduction of the absolute value of Vts as the channel length decreases, which results in a poorer controllability of the transistor.
The prior approaches to this problem include 1) to scale the gate oxide thickness, 2) to increase the channel ion implant dose, and 3) to employ a recently developed large angle package implant technique.
The first two approaches suffer from additional degradation in device reliability and performance, such as lower drive current resulted from reduced carrier mobility and lower speed resulted from increased junction capacitance; whereas the third approach, being a rather complicated process, is difficult implement for volume production.
The same situation is true for metal-insulator-semiconductor (MIS) field-effect transistors in general, as well as silicon-on-insulator (SOI) transistors.
Hence, there has been a need in the art for a simpler and more effective method suitable for volume production to provide both saturation threshold voltage (Vts) roll-off control and speed improvement without introducing additional degradation in device reliability and performance, such as lower drive current and lower device lifeline.